研究機構近期對ASIC龍頭創意的獲利展望進行大幅調整，將其 2026 年與 2027 年的每股純益預估分別上修至 54.6 元與 113.1 元。這項轉向反映了生成式人工智慧底層架構的根本位移：隨著模型從單純的訓練走向代理式AI與思考鏈推論，運算負載由純粹的圖形處理器，外溢至高頻寬的客製化晶片與專屬處理器。與此同時，北美雲端服務巨頭加速將晶片外包模式由傳統統包轉為COT模式。這場晶片設計範式的轉換，不僅徹底消除設計廠的晶圓庫存跌價包袱，更讓位處台積電生態圈核心的特定業者，迎來產品結構與獲利能力的質變時刻。Research institutions have sharply revised their earnings outlook for leading ASIC design service provider Global Unichip Corp. (GUC), lifting their 2026 and 2027 earnings per share projections to NT$54.6 and NT$113.1, respectively. This reassessment reflects a fundamental architectural pivot in generative AI: as workloads shift from pure training toward agentic AI and chain-of-thought inference, computational intensity is spilling over from pure-play GPUs to high-bandwidth custom ASICs and dedicated accelerators. Concurrently, North American cloud service providers are accelerating a structural shift in their chip procurement models, moving from turnkey solutions to customer-owned tooling (COT). This paradigm shift not only eliminates the burden of wafer inventory markdowns for design service houses, but also positions select players anchored at the core of the TSMC ecosystem for a qualitative transformation in both product mix and long-term earnings power.

運算架構位移推動外包轉向COT模式Architectural Shifts Drive Transition to COT Model

代理式AI運作依賴密集的邏輯決策與上下文檢索，這項特性顛覆了伺服器內部的硬體平衡，促使中央處理器與圖形處理器的配置比例，從過往的 0.5 比 1 大幅攀升到 0.8 至 1.4 比 1。包含微軟自研晶片在內的超大規模資料中心客戶，正陸續放棄傳統的統包代工，轉而由客戶自行主導底層架構，並將後端實體設計、先進封裝整合委外給設計服務夥伴。在這種COT合作架構下，設計業者擺脫了晶圓採購的跌價與存貨滯銷壓力，獲利來源轉化為利潤率更高的委託設計服務費用，以及涵蓋先進封裝與高速互連技術的專利授權收入，實質帶動獲利體質的結構性優化。Agentic AI depends heavily on intensive logical decision-making and context retrieval. This dynamic has upended internal server topologies, pushing the deployment ratio of CPUs to GPUs from historical levels of 0.5:1 up to between 0.8:1 and 1.4:1. Hyperscale cloud customers, including Microsoft with its in-house silicon initiatives, are increasingly abandoning traditional turnkey foundry arrangements in favor of retaining core architectural control, outsourcing only backend physical design and advanced packaging integration to design service partners. Under this COT framework, design houses shed the risks of wafer inventory writedowns and obsolete stock. Instead, their revenue streams pivot toward higher-margin non-recurring engineering (NRE) fees and IP licensing for advanced packaging and high-speed interconnects, driving a structural expansion in profitability margins.

獲利預期在 3 年節點出現巨大分歧Three-Year Earnings Trajectories Diverge Sharply

模式轉變引發市場高度關注，但機構法人對獲利爆發的時間點與續航力產生嚴重分歧。統計近 30 日研究報告，5 家大型機構對創意 2026 年每股純益的預估落在 52.06 元至 54.76 元之間，差異幅度僅約 5.2%，顯示中期營運能見度極高。然而，針對 2027 年的每股純益預估卻拉出 110.30 元至 214.50 元的極端區間，高低差距逼近 100%。樂觀論點押注北美車用與雲端客戶的先進製程專案如期在 2027 年進入量產放量期；持審慎態度的機構則提醒，短期毛利率已受到產品組合變動影響而出現波動，且營收若過度集中於單一雲端巨頭，一旦演算法架構改弦易轍，研發遞延風險不容輕忽。While this structural pivot has captivated the market, institutional investors remain sharply divided over the timing and durability of the resulting earnings inflection. Research reports issued over the past thirty days show five major institutions projecting GUC's 2026 EPS within a tight band of NT$52.06 to NT$54.76—a variance of just 5.2%, signaling strong medium-term visibility. For 2027, however, EPS estimates diverge wildly from NT$110.30 to NT$214.50, an extreme spread approaching 100%. The bull case bets that advanced-node projects for North American automotive and hyperscale cloud customers will hit volume production on schedule by 2027. Conversely, more conservative houses caution that near-term gross margins have grown volatile amid product mix transitions, warning that heavy revenue concentration in a single cloud titan leaves little room for error should algorithmic architectures shift or development cycles face delays.

先進封裝與互連技術構築產業護城河Packaging and Interconnects Form Competitive Moats

在同一晶圓代工體系下，特殊應用晶片設計廠的競爭格局正隨著製程微縮而加速分化。相較於同業在先進製程更迭中面臨的良率爬坡與驗證考驗，創意仰賴母公司台積電在先進封裝產能上的穩定配額支援，以及自主研發的GLink高速互連矽智財，在超高頻寬需求的客製化推論晶片領域築起高聳的客戶轉換障礙。這類高效能運算專案不僅需要頂尖的實體設計能力，更要求晶片與先進封裝技術具備高度相容性。隨著北美各大資料中心客戶逐步將推論晶片推向先進製程節點，設計服務廠掌握的封裝專利與投片資源，已成為決定次世代開案市占率消長的核心戰略資產。Within the same foundry ecosystem, competitive differentiation among ASIC design service firms is accelerating as process geometries shrink. While peers grapple with yield ramps and validation hurdles across leading-edge nodes, GUC draws on guaranteed allocations of advanced packaging capacity from its parent company, TSMC, alongside its proprietary GLink high-speed interconnect IP. Together, these assets erect formidable switching barriers in custom inference accelerators where ultra-high memory bandwidth is paramount. High-performance computing projects of this caliber require not only world-class physical design execution, but also tight co-design integration with advanced packaging topologies. As North American hyperscalers push custom inference silicon onto leading-edge nodes, proprietary packaging IP and guaranteed wafer allocations have become decisive strategic assets in capturing next-generation tape-outs.

本刊判斷，ASIC設計服務業的評價核心正從純粹的開案數量，轉向先進製程投片放量的實質變現能力。接下來的觀察重點在於，雲端大客戶自研處理器在晶圓代工廠的實質投片爬坡動能，以及設計業者能否在營收規模快速放大的同時，維持委託設計業務的高毛利水準，藉此驗證市場對獲利倍增預期的合理性。In our view, the valuation framework for ASIC design service providers is shifting decisively from headline project counts to the tangible execution of volume production ramps at advanced nodes. Crucial markers ahead include the actual production ramp of in-house hyperscale silicon at foundries and whether design firms can defend high NRE gross margins as overall top-line revenue scales, thereby validating market expectations of an earnings doubling.